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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6458 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 gsm 3 v receiver if subsystem functional block diagram features fully compliant with standard and enhanced gsm specification C12 dbm input 1 db compression point C2 dbm input third order intercept 10 db ssb noise figure (330 v ) dcC400 mhz rf and lo bandwidths linear if amplifier linear-in-db and stable over temperature voltage gain control quadrature demodulator onboard phase-locked quadrature oscillator demodulates ifs from 5 mhz to 50 mhz low power 9 ma at midgain 1 m a sleep mode operation 3.0 v to 3.6 v operation interfaces to ad7013, ad7015 and ad6421 baseband converters 20-lead ssop general description the AD6458 is a 3 v, low power receiver if subsystem for operation at input frequencies as high as 400 mhz and ifs from 5 mhz up to 50 mhz. it is optimized for operation in gsm, dcs1800 and pcs1900 receivers. it consists of a mixer, if amplifier, i and q demodulators, a phase-locked quadrature oscillator, precise agc subsystem, and a biasing system with external power-down. the low noise, high intercept mixer of the AD6458 is a doubly-balanced gilbert cell type. it has a nominal C12 dbm input-referred 1 db compression point and a C2 dbm input- referred third-order intercept. the mixer section of the AD6458 also includes a local oscillator (lo) preamplifier, which lowers the required lo drive to C16 dbm. the gain control input accepts an external gain-control voltage input from an external agc detector or a dac. it provides an 80 db gain range with 27 mv/db gain scaling. the i and q demodulators provide inphase and quadrature baseband outputs to interface with analog devices ad7013 (is54, tetra, msat) and ad7015 and ad6421 (gsm, dcs1800, pcs1900) baseband converters. an onboard quadrature vco which is externally phase-locked to the if signal drives the i and q demodulators. this locked reference signal is normally provided by an external vctcxo under the control of the radios digital processor. the AD6458 can also provide demodulation of n-psk and n-qam in many non- tdma systems when used with external analog carrier recovery systems such as the costas loop. finally, the vco can be phase-locked to a frequency which is deliberately offset from the if, as in the case of a beat-frequency oscillator (bfo), result- ing in the product detection of cw or ssb. the AD6458 uses supply voltages from 3.0 v to 3.6 v over the temperature range of C40 c to +85 c. operation is enabled by a cmos logical level; response time is typically <80 m s. when disabled, the standby current is reduced to 1 m a. the AD6458 comes in a 20-lead shrink small outline (ssop) surface-mount package. bpf lo i q agc fref rf AD6458 plo
C2C rev. 0 AD6458Cspecifications (@ t a = +25 8 c, v p = 3.0 v, gref = 1.2 v, unless otherwise noted) parameter conditions min typ max units mixer maximum rf and lo frequency 400 mhz agc conversion gain variation 0.2 v < v g < 2.25 v, z s = 50 w , z load = 330 w C8.5 to +9.5 db input rf signal range C95 C15 dbm input 1 db compression point @ v g = 0.2 v, z s = 50 w , z load = 330 w C11 dbm input third-order intercept @ v g = 0.2 v, z s = 50 w , z load = 330 w C2 dbm ssb noise figure 1 @ z s =1 k w , f rf = 83 mhz, f lo = 96 mhz at C16 dbm 9 db mixer output bandwidth at mxop @ C3 db, z load = 330 w 55 mhz if amplifiers agc gain variation 0.2 v < v g < 2.25 v C9 to +48 db input referred noise ac short circuit input 3 nv/hz input resistance @ v g = 0.2 v 5 k w bandwidth @ C3 db 50 mhz i and q demodulators demodulation gain 17 db output voltage range irxp, irxn, qrxp, qrxn 0.3 v p C 0.2 v output voltage common-mode level (not power supply dependant) 1.5 v output offset voltage differential C150 +150 mv output offset voltage variation differential, over gain and temperature range 2 1mv output offset voltage variation differential, for 0.5 v < v g < 2.4 v and C25 c < t a < +85 c (see note 2) 0.5 mv error in quadrature if = 13 mhz 1.5 3.7 degree amplitude match 0.25 db i/q output bandwidth c load = 10 pf 2 mhz output resistance each pin 4.7 k w gain control total gain control range mixer + if + demod, 0.2 v < v g < 2.25 v 75 db control voltage range at gain 0.2 2.4 v gain scaling 23 27 32 mv/db gain law conformance 0.5 db bias current at gref 0.5 m a input resistance at gain 20 k w pll frequency range 5 40 mhz phase noise 0.5 degree rms acquisition time if = 13 mhz, using ceramic filter 80 m s input drive level (fref) 100 vpos mv power-down interface logical threshold power-up on logical high 1.5 v input current for logical high 75 m a turn on response time to fully meet specifications 80 150 m s stand by current (see note 3) 1 8 m a power supply supply range 3.0 3.3 3.6 v worst case supply current @ v gain = 0.2 v, t a = +85 c, v p = 3.6 v 4 16.5 22 ma supply current @ v gain = 1.2 v 9 ma operating temperature t min to t max C40 to +85 c notes 1 including if noise and using 13 mhz ceramic filter, at v gain = 0.2 v. 2 histograms of demodulator offset voltage variation in gain and temperature can be found in figures 23 to 27. 3 max value represent the value at six times the standard deviation, in the worst case condition (t a = +85 c). the value at three times the standard deviation is 5 m a. 4 max value represent the value at six times the standard deviation. the value at three times the standard variation is 19 ma. specifications subject to change without notice.
AD6458 C3C rev. 0 absolute maximum ratings 1 supply voltage vps1, vps2 to com1, com2 . . . . . +3.6 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 600 mw operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering (60 sec) . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 20-lead ssop package: q ja = 126 c/w. ordering guide temperature package package model range description option AD6458ars C40 c to +85 c 20-lead shrink small outline rs-20 pin function descriptions pin pin number label description function 1 fref frequency reference input demodulation lo input. may be 3 v cmos input or >100 mv ac coupled for lowest stand by current. 2 com1 common 1 ground. 3 prup power-up input cmos compatible power up control; 0 = off, 3 v = on. 4 loip local oscillator input ac coupled lo input. only 50 mv drive needed, 500 mv max. 5 rflo rf low input usually connected to ac ground. 6 rfhi rf high input ac coupled, C 109 dbv to C29 dbv rf input from 1 k w filter for optimal operation. 7 com2 common 2 ground. 8 gref gain reference input high impedance input, sets gain scaling, typically 1.2 v. 9 mxop mixer output output of the mixer. 10 nc not internally connected. should be grounded. 11 ifip if input plus differential input of variable gain amplifier. 12 ifim if input minus differential input of variable gain amplifier. 13 gain gain control input 0.2 vC2.4 v using 3 v supply. max gain at 0.2 v. 14 qrxn q output negative differential q output. 15 qrxp q output positive differential q output. 16 irxn i output negative differential i output. 17 irxp i output positive differential i output. 18 vps2 vpos supply 2 supply voltage. 19 fltr ppl loop filter series rc loop filter, connected to vps2. 20 vps1 vpos supply 1 supply voltage. pin connection 20-lead ssop (rs-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD6458 fref irxp vps2 fltr vps1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop nc ifip ifim gain nc = no connect warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6458 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD6458 C4C rev. 0 10 9 8 1 2 3 4 7 6 5 14 13 12 11 17 16 15 20 19 18 AD6458 fref irxp vsp2 fltr vsp1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop ifip ifim gain r1 20k w vpos c1 0.1? c10 1nf r8 1k w c11 0.1? c10 0.1? (bottom) c7 0.01? c8 0.01? r6 50 w r7 50 w r4 54.9 w fref r9 50 w r2 50 w prup loip rfhi gref r3 50 w c12 220pf c2 1nf c4 1nf c3 1nf vpos irxp qrxn qrxp irxn gain mxop ifip ifim r5 open c6 1nf r10 301 w figure1. characterization board c7 0.1pf v n r4 50 w i out c6 0.1pf v p r3 50 w q out gain fref vpos gref gref prup loip rfip mxop ifip ifim irxp irxn qrxp qrxn gain AD6458 characterization board prup loip rfip fref vpos r5 50 w ifin r1 100 w mxop 1 2 3 4 8 7 6 5 v p v n a=1 gm gm ad830 c5 0.1pf v n c4 0.1pf v p 1 2 3 4 8 7 6 5 v p v n a=1 gm gm ad830 c8 0.1pf v n c9 0.1pf v p 1 2 3 4 8 7 6 5 v p v n a=1 gm gm ad830 r6 50 w c10 0.1pf v n c11 0.1pf v p 1 2 3 4 8 7 6 5 v p v n a=1 gm gm ad830 figure 2. characterization test set
AD6458 C5C rev. 0 hp8657b synthesizer rf out mod i/o 10mhz out 10mhz in sync i eee AD6458 mother board prup vpos vin vp fref loip rfip gref mxop ifin iout qout gain hp6237 +5v ?v com +15v hp34401 hi lo i hi dmm i eee hp663x power supply i eee hi lo hp8657b synthesizer rf out mod i/o 10mhz out 10mhz in sync i eee dp8200 dc source hi f hi s lo f lo s gnd i eee dp8200 dc source i eee hi f hi s lo f lo s gnd cal out rf i/p i eee 28 volt sweep out hp8593e analyser spectrum hp8657b synthesizer rf out mod i/o 10mhz out 10mhz in sync i eee figure 3. mixer characterization setup c9 10nf prup c5 0.1? 10 9 8 1 2 3 4 7 6 5 14 13 12 11 17 16 15 20 19 18 AD6458 fref irxp vsp2 fltr vsp1 com1 prup loip qrxn qrxp irxn rflo rfhi com2 gref mxop ifip ifim gain vpos c1 0.1? c10 1nf r8 1k w c11 0.1? fref r2 50 w loip rfhi gref r1 50 w c12 220pf c2 1nf c4 1nf c7 1nf vpos irxp qrxn qrxp irxn gain r5 330 w c13 10nf bpf2 figure 4. typical connection diagram
AD6458 C6C rev. 0 rf frequency ?mhz 22 12 6 80 120 noise figure ?db 160 200 240 280 320 360 400 440 20 14 10 8 18 16 f if = 13mhz, z s = 50 w f if = 26mhz, z s = 50 w f if = 13mhz, z s = 400 w figure 5. mixer noise figure vs. rf frequency noise figure ?db percentage 35 0 7.0 8.4 7.2 7.4 7.6 7.8 8.0 8.2 30 20 15 10 5 25 = 7.7db = 0.26db figure 6. mixer noise figure histogram, r s = 1 k w , f rf = 83 mhz, f if = 13 mhz rf frequency ?mhz resistance ?k w 2.0 1.6 0 50 550 100 150 200 250 300 350 400 450 500 1.2 0.8 0.4 5.5 cap ?pf 5.0 3.0 4.5 4.0 3.5 c sh , v gain = 0.2v r sh , v gain = 2.2v c sh , v gain = 1.0v r sh , v gain = 1.0v c sh , v gain = 2.2v r sh , v gain = 0.2v figure 7. mixer input impedance vs. rf frequency, v pos = 3.0 v, t a = +25 c rf frequency ?mhz conversion gain ?db 15 0 ?5 50 550 100 150 200 250 300 350 400 450 500 10 5 ? ?0 v gain = 0.2v v gain = 1.2v v gain = 2.2v figure 8. mixer conversion gain vs. rf frequency, t a = +25 c, v pos = 3.0 v, v ref =1.2 v, f if =13 mhz gain ?db if frequency ?mhz 12 ? ?0 10 54 14 18 22 26 30 34 38 42 46 50 10 0 ? ? 8 4 6 2 ? v gain = 0.2v v gain = 1.5v v gain = 2.2v figure 9. mixer conversion gain vs. if frequency, t a = +25 c, v pos = 3 v, v ref = 1.2 v, f rf = 250 mhz v gain ?volts gain ?db 15 10 ?5 0 2.5 0.5 1.0 1.5 2.0 5 0 ? ?0 v pos = 3v to 3.6v t a = ?5 c to +85 c figure 10. mixer conversion gain vs v gain , v ref = 1.2 v, f if =13 mhz, f rf = 83 mhz
AD6458 C7C rev. 0 v gain ?volts ? ? ?5 0 2.5 0.5 1.0 1.5 2.0 ?1 ?2 ?3 ?4 ?0 v pos = 3.6v t a = +85 c v pos = 3.0v t a = +85 c v pos = 3.6v t a = +25 c v pos = 3.0v t a = +25 c v pos = 3.0v t a = ?5 c v pos = 3.0v t a = ?0 c input ?dbm (referred to 50 w ) figure 11. mixer input 1 db compression point vs. v gain , v ref = 1.2 v, f rf = 83 mhz, f if = 13 mhz intermediate frequency ?db 70 0 545 10 15 20 25 30 35 40 60 40 30 20 10 50 v gain = 0.2v v gain = 1.0v v gain = 1.5v v gain = 2.25v if amp/demod gain ?db figure 12. if amplifier and demodulator gain vs. frequency, t a = +25 c, v pos = 3.0 v, v ref =1.2 v v gain ?volts gain ?db 70 60 ?0 0 2.5 0.5 1.0 1.5 2.0 30 20 10 0 50 40 t a = ?0 c to +85 c figure 13. if amplifier and demodulator gain vs. v gain , t a = +25 c, v pos = 3.0 v, f if = 13 mhz, v ref = 1.2 v if input ?dbm (referred to 50 w ) v gain ?volts ? ?0 ?0 0 2.5 0.5 1.0 1.5 2.0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 t a = ?0 c t a = ?5 c t a = +25 c t a = +85 c figure 14. if amplifier/demodulator input 1 db compres- sion point vs. v gain , f if =13 mhz, v ref = 1.2 v, t a = +25 c, v pos = 3.0 v if frequency ?mhz 12000 6000 0 0 100 10 resistance ? w 20 30 40 50 60 70 80 90 10000 8000 4000 2000 r shunt, v gain = 2.2v c shunt, v gain = 1.0v r shunt, v gain = 1.0v r shunt, v gain = 0.2v c shunt, v gain = 2.2v c shunt, v gain = 0.2v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 capacitance ?pf figure 15. if amplifier input impedance vs. frequency, t a = +25 c, v pos = 3.0 v, v ref = 1.2 v gain voltage ?volts 1 0.8 0 0 2.5 0.5 1 1.5 2 0.2 ?.6 ?.8 ? 0.6 0.4 ?.4 ?.2 mixer error ?db if amp/demod figure 16. AD6458 gain error vs. gain control voltage, representative part
AD6458 C8C rev. 0 f ref frequency ?mhz quad_error 4.0 0 10 55 15 20 25 30 35 40 45 50 3.5 2.0 1.5 1.0 0.5 3.0 2.5 figure 17. demodulator quadrature error vs. f ref frequency, t a = +25 c, v pos = 3.0 v percentage error ?degrees 16 6 0 1.5 2.9 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.0 14 8 4 2 12 10 = 2.1d = 0.3d figure 18. demodulator quadrature error histogram t a = +25 c, v pos = 3.0 v. f if = 13 mhz carrier frequency ?khz phase noise ?dbc ?0 ?5 ?20 0.1 10k 1 10 100 1k ?00 ?05 ?10 ?15 figure 19. pll phase noise vs. frequency, v pos = 3 v, c fltr = 1 nf, r fltr = 1 k w , f ref = 13 mhz pll frequency ?mhz fltr pin voltage referenced to v pos ?volts ?.1 ?.5 555 10 15 20 25 30 35 40 45 50 ?.3 ?.5 ?.7 ?.9 ?.1 ?.3 figure 20. pll loop voltage at fltr pin (kvco) vs. frequency v gain ?volts ?0 ?5 ?5 0 2.5 0.5 1.0 1.5 2.0 ?0 ?5 ?0 ?0 ?0 ?5 ?0 ?5 ?5 input ?dbm (referred to 50 w - ie. +10dbm -> 2v p-p) figure 21. system [(mixer + if ceramic filter + if ampli- fier + demodulator)] input 1 db compression point vs. v gain , t a = +25 c, v pos = 3.0 v, f if = 13 mhz, f rf = 83 mhz, v ref = 1.2 v v gain ?volts gain ?db 80 70 ?0 0 2.5 0.5 1.0 1.5 2.0 40 10 0 ?0 60 50 20 30 figure 22. system (mixer + if ceramic filter + if amplifier + demodulator) conversion gain vs. v gain , t a = +25 c, v pos = 3.0 v, f if = 13 mhz, f rf = 83 mhz, v ref = 1.2 v
AD6458 C9C rev. 0 percentage variation C mv 100 30 0 C4.9 C3.9 C2.9 C1.9 C0.9 0.1 1.1 2.1 3.1 4.1 90 40 20 10 70 50 80 60 = 0.03mv = 0.4mv figure 23. demodulation output offset voltage variation histogram with variation referred to offset at v gain = 1.2 v and t a = +25 c, v gain = 2.25 v and t a = +25 c variation C mv percentage 80 30 0 C2.9 3.1 C2.4 C1.9 C1.4 C0.9 C0.4 0.1 0.6 1.1 1.6 2.1 2.6 70 40 20 10 60 50 = 0.1mv = 0.6mv figure 24. demodulation output offset voltage variation histogram with variation referred to offset at v gain = 1.2 v and t a = +25 c, v gain = 0.5 v and t a = +25 c c percentage variation C mv 50 15 0 C4.9 5.1 C3.9 C2.9 1.1 C1.9 C0.9 0.1 2.1 3.1 4.1 45 20 10 5 35 25 40 30 = 0.04mv = 1.1mv percentage variation C mv 50 15 0 C4.9 5.1 C3.9 C2.9 1.1 C1.9 C0.9 0.1 2.1 3.1 4.1 45 20 10 5 35 25 40 30 = 0.04mv = 1.1mv figure 25. demodulation output offset voltage variation histogram with variation referred to offset at v gain = 1.2 v and t a = +25 c, v gain = 0.2 v and t a = +25 c percentage offset drift C mv 16 8 0 C10 10 C8 C6 C4 C2 0 2 4 6 8 14 12 4 2 10 6 = 0.9mv = 3.4mv figure 26. demodulation output offset voltage variation histogram with variation referred to offset at v gain = 1.2 v and t a = +25 c, v gain = 0.2 v and t a = C25 c offset drift C mv percentage 30 15 0 C10 10 C8C6C4C202468 25 20 10 5 = C0.04mv = 3.6mv figure 27. demodulation output offset voltage variation histogram with variation referred to offset at v gain = 1.2 v and t a = +25 c, v gain = 0.2 v and t a = +85 c v gain C volts supply current C ma 18 16 6 0 2.5 0.5 1.0 1.5 2.0 14 12 10 8 v pos = 3.0v, t a = +85 c v pos = 3.6v, t a = +85 c v pos = 3.6v, t a = +25 c v pos = 3.6v, t a = C40 c figure 28. power supply current vs. gain control volt- age, v ref = 1.2 v
AD6458 C10C rev. 0 product overview the AD6458 provides most of the active circuitry required to realize a complete low power, single-conversion superhetero- dyne receiver, or the latter part of a double-conversion receiver, at input frequencies up to 400 mhz, with an if from 5 mhz to 50 mhz. the internal i/q demodulators, and their associated phase-locked loop, support a wide variety of modulation modes, including n-psk, n-qam, and gmsk. a single positive supply voltage of 3.3 v is required (3.0 v minimum, 3.6 v maximum) at a typical supply current of 9 ma at midgain. in the following discussion, v pos will be used to denote the power supply volt- age, which will be assumed to be 3.3 v. figure 31 shows the main sections of the AD6458. it consists of a variable-gain uhf mixer and linear two-stage if strip, which together provide a calibrated voltage-controlled gain range of more than 76 db, followed by dual quadrature demodulators. these are driven by inphase and quadrature clocks generated by a phase-locked loop (pll), which is locked to a corrected external reference. a cmos-compatible power-down interface completes the AD6458. v gain ?volts v prup ?volts 2.0 1.9 1.0 0 2.5 0.5 1.0 1.5 2.0 1.6 1.3 1.2 1.1 1.8 1.7 1.4 1.5 t a = ?0 c t a = ?5 c t a = +25 c t a = +85 c figure 29. minimum power-up voltage vs v gain , v pos = 3.0 v, v ref = 1.2 v mixer the uhf mixer is an improved gilbert-cell design, and can operate from low frequencies (it is internally dc-coupled) up to an rf input of 400 mhz. the dynamic range at the input of the mixer is determined at the upper end by the maximum input signal level of 56 mv (C15 dbm in 50 w between rfhi and rflo) up to which the mixer remains linear and, at the lower end, by the noise level. it is customary to define the linearity of a mixer in terms of the 1 db gain-compression point and third- order intercept, which for the AD6458 are C12 dbm and C2 dbm, respectively, in a 50 w system. the mixers rf input port is differential; that is, pin rflo is functionally identical to rfhi, and these nodes are internally biased. the rf port can be modeled as a parallel rc circuit as shown in figure 30. rfhi rflo c sh r sh figure 30. mixer port modeled as a parallel rc network the local oscillator (lo) input is internally biased at v p C 0.8 v and must be ac coupled. the lo interface includes a preampli- fier which minimizes the drive requirements, thus simplifying the oscillator design and reducing lo leakage from the rf port. the lo requires a single-sided drive of 50 mv, or C16 dbm in a 50 w system. for operation above 300 mhz noise figure can be improved by increasing the lo level. the output of the mixer is single ended with a 330 w impedance for driving ceramic filters. the conversion gain is measured between the mixer input and the input of this filter, and varies between C9 db and +10 db as a function of the voltage at pin gain. the maximum permissible signal level at pin mxop is deter- mined by the maximum gain control voltage. the mixer output port is shown in figure 32. vps1 rfhi AD6458 mxop ifip ifim 0 90 4.7k w 4.7k w 4.7k w 4.7k w agc voltage bias circuit vps2 prup rflo loip irxp irxn fref fltr qrxp qrxn gain gref 19 20 13 14 15 16 18 6 7 8 1 2 3 4 5 com1 com2 9 12 rf input ?5dbm to ?5dbm 330 w 0.1? lo input ?6dbm 17 11 gain tc compensation pll 13mhz ceramic bandpass filter figure 31. functional block diagram
AD6458 C11C rev. 0 mxp 275 w 275 w 25k w v bias 160k w mxm vpos from mixer core mxop 330 w figure 32. mixer output port if amplifier most of the gain in the AD6458 resides in the if amplifier strip, which comprises two stages. both are fully differential and each has a gain span of 26 db for the agc voltage range of 0.2 v to 2.25 v. thus, in conjunction with the variable gain of the mixer, the total gain span is 76 db. the overall if gain varies from C9 db to 48 db for the nominal agc voltage of 0.2 v to 2.25 v. maximum gain is at v gain = 0.2 v. the if input is differential at ifip and ifim. figure 33 shows a simplified schematic of the if interface modeled as parallel rc network. the ifs small-signal bandwidth is approximately 50 mhz from ifip and ifim through the demodulator. ifhi iflo c sh r sh figure 33. if amplifier port modeled as a parallel rc network gain scaling the AD6458s overall gain, expressed in decibels, is linear with respect to the agc voltage v gain at pin gain. the gain of all sections is maximum when v gain is 0.2, and falls off as the bias is increased to v gain = 2.25 and is independent of the power supply voltage. the gain of all stages changes simultaneously. the AD6458s gain scaling is also temperature compensated. the gain pin of the AD6458 is an input driven by an external low impedance voltage source, normally a dac, under the control of radios digital processor. the gain-control scaling is directly proportional to the reference voltage applied to the pin gref and is independent of the power supply voltage. when this input is set to the nominal value of 1.2 v, the scale is nominally 27 mv/db (37 db/v). under these conditions, 76 db of gain range (mixer plus if) corresponds to a control voltage of 0.2 v <= v g <= 2.25 v. the final centering of this 2.05 v range depends on the insertion losses of the if filters used. pin gref can be tied to an external voltage reference, v ref , provided, for example, by a ad1580 (1.21 v) voltage reference. AD6458 irxp irxn qrxp qrxn gref gain fref ad6421 100pf 100pf 100pf 100pf 0.1? 160 w 1nf vctcxo irxp irxn qrxp qrxn brefout brefcap agc dac afc dac figure 34. interfacing the AD6458 to the ad6421 baseband converter when using the analog devices ad7013 (is54, tetra and satellite receiver applications) and ad7015 or ad6421 (gsm, dcs1800, pcs1900) baseband converters, the external ref- erence may also be provided by the reference output of the baseband converters. the interface between the AD6458 and the ad6421 baseband converter is shown in figure 34. the ad6421 baseband converter provides a v ref of 1.23 v; an auxiliary dac in the ad6421 can be used to generate the agc voltage. since it uses the same reference voltage, the numerical input to this dac provides an accurate rssi value in digital form, no longer requiring the reference voltage to have high absolute accuracy. i/q demodulators both demodulators (i and q) receive their inputs internally from the if amplifiers. each demodulator comprises a full-wave synchronous detector followed by an 8 mhz, two-pole low-pass filter, producing differential outputs at pins irxp and irxn, and qrxp and qrxn. using the i and q demodulators for ifs above 50 mhz is precluded by the 5 mhz to 50 mhz range of the pll used in the demodulator section. the i and q outputs are differential and can swing up to 2.2 v p-p at the low supply voltage of 3.0 v. they are nominally centered at 1.5 v independently of power supply. they can therefore directly drive the rx adcs in the ad6421 baseband converter, which require an amplitude of 1.23 v to fully load them when driven by a differential signal. the conversion gain of the i and q demodulators is 17 db. for ifs of less than 8 mhz, the on-chip low-pass filters (8 mhz cutoff) do not adequately attenuate the if or feedthrough prod- ucts; the maximum input voltage must thus be limited to allow suffi cient headroom at the i and q outputs, not only for the de- sired baseband signal but also the unattenuated higher order demodulation products. these products can be removed by an external low-pass filter. a simple 1-pole rc filter, with its cor- ner above the modulation bandwidth, is sufficient to attenuate undesired outputs. the design of the rc filter is eased by the 4.7 k w resistor integrated at each i and q output pin.
AD6458 C12C rev. 0 i/q convention the AD6458 is a complete if receive subsystem. although not a requirement for using the AD6458, most applications will use a high-side lo injection on pin loip (pin 4) of the mixer. the i and q convention is such that when a spectrum with i leading q is presented to the input of the mixer, and a high-side lo is presented on pin loip, i still leads q at the baseband output of the AD6458. phase-locked loop the demodulators are driven by quadrature signals provided by a variable frequency quadrature oscillator (vfqo), phase- locked to a reference signal applied to pin fref. when this signal is at the if, in-phase and quadrature baseband outputs are generated at the i output (irxp and irxn) and q output (qrxp and qrxn), respectively. the quadrature accuracy of this vfqo is typically 2 at 13 mhz. a simplified diagram of the fref input is shown in figure 35. fref 50? ptat v pos 5k w 20k w 5k w figure 35. simplified schematic of the fref interface outline dimensions dimensions shown in inches and (mm). c3052C2C4/97 printed in u.s.a. 20-lead plastic ssop (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 the vfqo operates from 5 mhz to 50 mhz and is controlled by the voltage between v pos and fltr. in normal operation, a series rc network, forming the pll loop filter, is connected from fltr to v pos . the use of an integral sample-hold system ensures that the frequency-control voltage on pin fltr re- mains held during power-down, so reacquisition of the carrier occurs in less than 80 m s. in practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. this is typically < 80 m s for a quadrature phase error of 3 at an if of 13 mhz. note that the vfqo always provides quadrature between its own i and q outputs, but the phasing between it and the reference carrier will swing around the final value during the plls set- tling time. bias system the AD6458 operates from a single supply, v pos , usually 3.3 v, at a typical supply current of 9 ma at midgain and t a = +25 c. any voltage from 3.0 v to 3.6 v may be used. the bias system includes a fast acting active high cmos- compatible power-up switch, allowing the part to idle at 1 m a when disabled. biasing is generally proportional-to-absolute- temperature (ptat) to ensure stable gain with temperature. other special biasing techniques are used to ensure very accu- rate gain, stable over the full temperature range.

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